What is SystemVerilog Assertion (SVA)?

SVA is an integral part of IEEE-1800 SystemVerilog language, focusing on the temporal aspects of specification, modeling and verification. SVA allows sophisticated, multi-cycle assertions and functional checks to be embedded in HDL code. SVA allows simple HDL boolean expressions to be built into complex definitions of design behavior, which can be used for assertions, functional coverage, debug and formal verification.

This course gives you an in-depth introduction to the language. It starts with basic concepts but quickly moves on to advanced topics. Specifically we delve deep into SVASequences and show how complex temporal expressions can be built. We describe how to leverage on first_match operator to avoid unexpected threads leading to false alarms.

On the properties front we show how local variables help you model design characteristics.

We end this course with a detailed look at Sampling Semantics inSVA - this is unique in the industry as many courses do not cover this key concept.

Below is more detailed agenda.

• Introduction to Assertions & ABV

• Introduction to SystemVerilog

• Structure of an assertion

• Sequences and Properties in SVA

• Sequence repetition operators

• Composition operators for SVA Sequences

• Detecting first_match in ranged-temporal sequences

• Endpoint detection in temporal sequences

• Advanced Property operators

• Local Variables in SVA properties

• Scheduling Semantics - the secret of SVA's success