The practice test consists ofthe objective questions in the RTL design domain. The participant can choose these objective tests to test their fundamentals in the area of RTLdesign using Verilog/VHDL. Each practice test consist of 30 questions!

•Practice Test 1: RTL Design using Verilog for beginners : Duration : 60 minutes

•Practice Test 2 : RTL Design using VHDL for beginners : Duration : 60 minutes

The test covers the objectivequestions on the RTL design, simulation and synthesis. The tests can be useful to beginners in the area of RTL design, beginners in the area of VLSIdesign.

Each test has objective questions and each question carries single mark. To pass you need to score 60% marks for each test.

If you are electronics engineering graduates, postgraduates then you can opt for this course. If you are electronics, electrical engineering students with goal to pursue career in the VLSI/FPGA/ASIC design then you can enroll for this course.

What you need to do is that, read question carefully and try to use the basic foundation to answer the question. If your foundation of Digital Design and CMOS is strong then you will be able to score good marks.

If you are preparing for the competitive examinations in the electronics domain or VLSI interviews then also you can use this course as a tool to test your fundamentals!