The quiz "Test Your Fundamentals : RTL Design Using Verilog" has 60 questions and duration is 120 minutes. The objective of this quiz is to test your basics of RTLDesign and simulation fundamentals. The questions are based on the basics of Verilog, simulation, Verilog constructs, FSM design and logic inferred for the RTL. This course can be best tool for the students those who wish to appear for those who wish to pursue their career in the VLSI or FPGAdesigns!

Following are few highlights of the course:

This course has six tests and following are details !

1) Basics of Verilog : 10 Questions and Duration is 20 minutes

2) RTL design using Verilog : 10 Questions and Duration is 20 minutes

3) Simulation and testbenches : 10 Questions and Duration is 20 minutes

4) Logic inferred for the RTL design : 10 Questions and Duration is 20 minutes

5) Advanced topics and FSM : 10 Questions and Duration is 20 minutes

6) RTL Design and Synthesis : 10 Questions and Duration is 20 minutes

Each test has 10 questions and each question carries single mark.

If you are electronics engineering graduates, postgraduates then you can opt for this course. If you are electronics, electrical engineering, computer science students with goal to pursue career in the VLSI/FPGA/ASIC design then you can enroll for this course.

What you need to do is that, read question carefully and try to use the basic foundation to answer the question. If your foundation of RTLDesign using Verilog is strong then you will be able to score good marks.

If you are preparing for the VLSIinterviews as beginners then also you can use this course as a tool to test your fundamentals!